The present invention relates to the field of microelectronics and more particularly to methods for patterning microelectronic layers.
As integrated circuit memory devices such as dynamic random access memories (DRAMs) become more highly integrated, the space available for each memory cell on the substrate is reduced. Accordingly, the space available for memory cell capacitors is also reduced making it more difficult to maintain the desired memory cell capacitance as integration densities increase. It may be particularly difficult to provide desired memory cell capacitances using conventional dielectric materials such as nitride/oxide (NO) or Ta2O5.
There have thus been efforts to develop capacitor dielectric layers from materials having dielectric constants more than 100 times higher than that of NO. In particular, materials such as (Ba,Sr)TiO3 (xe2x80x9cBSTxe2x80x9d) and (Pb,Zr)TiO3 (xe2x80x9cPZTxe2x80x9d) have been used to provide dielectric layers for memory cell capacitors. Dielectric layers formed from these materials can thus be used to increase the capacitance of a memory cell capacitor without increasing the surface area of the capacitor electrodes. When using BST or PZT to provide capacitor dielectric layers, however, Pt is generally used to provide the capacitor electrodes because Pt is relatively inert to the oxidation which may occur as a result of the high diffusivity of BST and PZT.
Pt electrodes, however, may be difficult to pattern because Pt does not readily react with conventional etching chemicals, and Pt is not easily etched using dry etching techniques such as reactive ion etching. In other words, it may be difficult to pattern a platinum layer using a conventional reactive ion etch because the reactivity between the halogen gas used in a reactive ion etch and platinum is relatively low. Other metals such as Ru and Ir may also be difficult to pattern because they are also relatively inert.
Sputtering techniques using relatively high ion energies have been developed to pattern electrodes from layers of an inert material such as Pt. When etching Pt layers using ion sputtering, however, redeposits may be formed on the sidewall of the etching mask, and the slope of the sidewall of the platinum electrode formed thereby may be reduced. The sputter etching of Pt layers is discussed in the reference by Won Jong Yoo et al. entitled xe2x80x9cControl of Etch Slope During Etching of Pt in Ar/Cl2/O2 Plasmasxe2x80x9d, Jpn. J. Appl. Phys., Vol. 35, 1996, pp. 2501-2504, Part 1, No. 4B, April 1996. This reference is hereby incorporated herein in its entirety by reference. As discussed in this reference, the sidewall redeposits may remain even after ashing the photoresist mask off.
As further discussed in, the Yoo et al. reference, an etchant gas including a mixture of Ar and Cl2 with more than 50% Cl2 can be reused to reduce the sidewall redeposits. While the sidewall redeposits may be reduced, however, the mask may be damaged by the Cl2 gas. Accordingly, the slope of the sidewall of the etched platinum layer may be reduced.
Notwithstanding the methods discussed above, there continues to exist a need in the art for improved methods for patterning microelectronic layers.
It is therefore an object of the present invention to provide improved methods for patterning microelectronic layers.
This and other objects are provided according to the present invention by methods including the steps of forming an etching mask on a microelectronic layer wherein the etching mask defines exposed portions of the layer and wherein the etching mask has a notch in a sidewall thereof adjacent the microelectronic layer. The exposed portions of the microelectronic layer are then etched. Accordingly, a discontinuity will be provided between sidewall redeposits on the etching mask and the microelectronic layer being etched. The sidewall redeposits can thus be removed when removing the etching mask.
More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer of a first mask material on the layer to be etched, and forming a second patterned mask layer of a second mask material on the first patterned mask layer wherein the first and second mask materials are different and wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining a notch in the sidewall of the etching mask adjacent the layer to be etched. The first mask material can be Ti, TiN, or W, and the second mask material can be SiO2 or Si3N4. Moreover, the layer being etched can be Pt, Ir, Ru, BST, or PZT.
Alternately, the etching mask can be a negative photoresist mask. As a result of interference of light through a photomask used to pattern the photoresist mask, the negative photoresist will have a notch at a base thereof adjacent the layer to be etched.
According to another aspect of the present invention, a method can be provided for forming a capacitor for a microelectronic device. This method includes the steps of forming an interlayer dielectric on a microelectronic substrate wherein the interlayer dielectric has a contact hole therein exposing a portion of the microelectronic substrate, and forming a conductive via in the contact hole. A conductive layer is formed on the interlayer dielectric and on the conductive via opposite the microelectronic substrate. An etching mask is formed on the conductive layer opposite the microelectronic substrate wherein the etching mask defines exposed portions of the conductive layer and wherein the etching mask has a notch in a sidewall thereof adjacent the conductive layer. The exposed portions of the conductive layer are etched thereby providing a capacitor storage electrode on the interlayer dielectric and on the conductive via. The etching mask is then removed, and a capacitor dielectric layer is formed on the capacitor storage electrode opposite the microelectronic substrate. A capacitor plate electrode is formed on the capacitor dielectric layer opposite the storage electrode.
According to the methods discussed above, a notch can be provided in an etching mask thereby producing a discontinuity between sidewall redeposits on the etching mask and the layer being etched. These discontinuities thus allow the sidewall redeposits to be removed during the step of removing the etching mask. Moreover, the methods of the present invention can be used to provide improved storage electrodes for microelectronic capacitors.